AIRTIGHT BY DESIGN: THE V20 HARDWARE SPECIFICATION AUDIT

UPPER SECTION — 3-TIER HARDWARE LOGIC INSULATION
(Stacked block diagram: Tier 1 on top, Tier 3 on bottom.)

Tiered Logic Classification: hardware is divided into Tier 1 (XOR),
Tier 2 (FSM), and Tier 3 (ALU/FPU).
- "Allowed for Verification" arrow points at Tier 1 + Tier 2.

Prohibition of Tier 3 in Verification: semantic scrubbing and control
loops are restricted to non-Turing-complete logic tiers.

Instruction Stream Isolation: the verification signal avoids the
Floating-Point Unit (FPU) and instruction stream entirely.

LOGIC TIER SECURITY STATUS
  Tier 1   Combinational Logic (XOR)     Allowed for Verification
  Tier 2   Sequential Logic (FSM)        Allowed for Verification
  Tier 3   Turing-Complete (ALU/FPU)     Prohibited in Scrubber/GDC

LOWER SECTION — VERIFICATION & STRUCTURAL LOCKDOWN

Prefix XOR & Fishbone Propagation
- Tier 1 parent XORs propagate validation outward through a ShortRank tree.

Stride Polynomial Monitoring
- The system tracks the specific trajectory through memory to prevent
  recursive drift.

Geometric Trajectory Binding
- Process identity is bound to its specific geometric path through the
  memory grid.

SOURCE: NotebookLM